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MAXQ3180(2008) Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza
componentes Descripción
Fabricante
MAXQ3180
(Rev.:2008)
MaximIC
Maxim Integrated MaximIC
MAXQ3180 Datasheet PDF : 48 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Low-Power, Multifunction, Polyphase AFE
VRST1
VPOR
BROWNOUT DETECTION
BROWNOUT DETECTION (ALWAYS
ENABLED OUTSIDE OF STOP MODE)
FORCES RESET STATE. POR = 1
BROWNOUT DETECTION DISABLED
DURING STOP MODE.
NO RESET IS GENERATED.
BROWNOUT DETECTION DISABLED.
POR LEVEL CAUSES RESET.
tPOR
INTERNAL
RESET
STOP MODE
Figure 3. Brownout Reset
error of some kind causes the MAXQ3180 to lock up or
enter an endless execution loop, the watchdog timer
expires and triggers an automatic hardware reset. There
is no register flag to indicate to the master that a watch-
dog reset has occurred, but the RESET line strobes low
briefly. Because the reset causes the MAXQ3180 to re-
enter Initialization Mode, the IRQ line drops low.
The watchdog timer does not run during Stop Mode.
Software Reset
A software reset is initiated by the master by setting the
RST (STATUS0.4) bit to 1. When a software reset
occurs, the MAXQ3180 clears all registers to their
default states and returns to Initialization Mode, in the
same manner as if an external reset had taken place.
Unlike a hardware reset, however, a software reset does
not cause the MAXQ3180 to drive the RESET line low.
Power-Supply Monitoring
In addition to the hardware reset provided by the
power-on reset and brownout reset circuits, the
MAXQ3180 includes the capability to detect a low
power supply on the DVDD pin and alert the master
through the interrupt (IRQ) mechanism before a hard-
ware reset occurs. This function, which is always
enabled outside of Stop Mode, causes the RAM status
register flag PWRF (STATUS1.1) to be set to 1 whenev-
er DVDD drops below the VPFW trip point. Once PWRF
has been set to 1 by hardware, it can only be cleared
by the master (or by a system reset). Whenever PWRF
= 1, if the EPWRF interrupt masking bit is also set to 1,
the MAXQ3180 drives IRQ low to signal to the master
that an interrupt condition (in this case, a power-fail
warning) exists and requires attention.
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