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MAX6323HUT46

μP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset

Maxim Integrated 

MAX6323/MAX6324

START

SET WDI

LOW

SUBROUTINE OR

PROGRAM LOOP

SET WDI HIGH

RETURN

END

Figure 9. Watchdog Flow Diagram

μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

WDPO to MR Loopback

An error detected by the watchdog often indicates that

a problem has occurred in the μP code execution.

This could be a stalled instruction or a loop from which

the processor cannot free itself. If the μP will still respond

to a nonmaskable input (NMI), the processor can be

redirected to the proper code sequence by connecting the

WDPO output to an NMI input. Internal RAM data should

not be lost, but it may have been contaminated by the

same error that caused the watchdog to time out.

If the processor will not recognize NMI inputs, or if the

internal data is considered potentially corrupted when a

watchdog error occurs, the processor should be restarted

with a reset function. To obtain proper reset timing

characteristics, the WDPO output should be connected

to the MR input, and the RESET output should drive the

μP RESET input (Figure 10). The short 1ms WDPO pulse

output will assert the manual reset input and force the

RESET output to assert for the full reset timeout period

(100ms min). All internal RAM data is lost during the reset

period, but the processor is guaranteed to begin in the

proper operating state.

VCC

500pF

VCC

MAX6323

MAX6324

RESET

MR

WDI

GND WDPO

*MAX6324 ONLY

Figure 10. WDPO to MR Loopback Circuit

*RPULLUP

VCC

µP

RESET

I/O

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