MAX5580A Ver la hoja de datos (PDF) - Maxim Integrated
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MAX5580A Datasheet PDF : 34 Pages
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Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
SCLK Frequency
fSCLK 2.7V < DVDD < 5.25V
SCLK Pulse-Width High
tCH
(Note 7)
20
SCLK Pulse-Width Low
tCL
(Note 7)
20
CS Fall to SCLK Fall Setup Time
tCSS
10
DSP Fall to SCLK Fall Setup Time
tDSS
10
SCLK Fall to CS Rise Hold Time
tCSH
5
SCLK Fall to CS Fall Delay
tCS0
10
SCLK Fall to DSP Fall Delay
tDS0
10
DIN to SCLK Fall Setup Time
tDS
12
DIN to SCLK Fall Hold Time
tDH
5
SCLK Rise to DOUT_ Valid
Propagation Delay
tDO1
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
TYP
MAX
20
30
SCLK Fall to DOUT_ Valid
Propagation Delay
tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode
30
CS Rise to SCLK Fall Hold Time
tCS1 MICROWIRE and SPI modes 0 and 3
10
CS Pulse-Width High
tCSW
45
DSP Pulse-Width High
tDSW
20
DSP Pulse-Width Low
tDSPWL (Note 8)
20
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100
DOUTRB Tri-State Time from CS
Rise
tDRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
20
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
tZEN
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
20
LDAC Pulse-Width Low
tLDL
Figure 5
20
LDAC Effective Delay
tLDS Figure 6
100
CLR, MID, SET Pulse-Width Low
tCMS Figure 5
20
GPO Output Settling Time
tGP
Figure 6
100
GPO Output High-Impedance
Time
tGPZ
100
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 _______________________________________________________________________________________
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