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MAX5411ETE

Dual, Audio, Log Taper Digital Potentiometers

Maxim Integrated 

Dual, Audio, Log Taper Digital Potentiometers

Table 5. Zero-Crossing Detection Register Bit Definitions for MAX5408/MAX5410

DATA BIT

VALUE

FUNCTION

0

Disable wiper W0A zero-crossing detection circuit

D4

1

Enable wiper W0A zero-crossing detection circuit

D3

“don’t care”

No change

0

Disable wiper W1A zero-crossing detection circuit

D2

1

Enable wiper W1A zero-crossing detection circuit

D1

“don’t care”

No change

D0

“don’t care”

No change

Table 6. Zero-Crossing Detection Register Bit Definitions for MAX5409/MAX5411

DATA BIT

VALUE

FUNCTION

0

Disable wiper W0A zero-crossing detection circuit

D4

1

Enable wiper W0A zero-crossing detection circuit

0

Disable wiper W0B zero-crossing detection circuit

D3

1

Enable wiper W0B zero-crossing detection circuit

0

Disable wiper W1A zero-crossing detection circuit

D2

1

Enable wiper W1A zero-crossing detection circuit

0

Disable wiper W1B zero-crossing detection circuit

D1

1

Enable wiper W1B zero-crossing detection circuit

D0

“don’t care”

No change

Table 7. Attenuation and Wiper Position

POSITION

0

1

2

3

4

.....

OUTPUT LEVEL (dB)

0

-2

-4

-6

-8

.....

30

31

MUTE

-60

-62

<-90

The digital output, DOUT, lags the digital input signal,

DIN by 8.5 clock cycles. Force CS high to disable

DOUT, placing DOUT in three-state mode. Force CS

low to enable DOUT and disable three-state mode.

Force CS high, after a word has been written to the

MAX5408–MAX5411 to make a readback request. The

next CS low period writes the requested data to DOUT.

A readback request overwrites any previous data in the

shift register. Note that the data appears at DOUT in

the order: A0, A1, A2, D4, D3, D2, D1, D0. A0 will be

available after the first high-to-low transition of SCLK

when CS is low. The input continues to load the shift

register while data is being read out of the MAX5408–

MAX5411. The input data appears at DOUT 8.5 clock

cycles later. A CS transition from low-to-high latches

the input data. For any control byte, the state of SCLK

must be the same for both CS low-to-high transitions

and CS high-to-low transitions in order to preserve the

data at DOUT while CS transitions. For proper opera-

tion, ensure that the input data remains valid on both

the SCLK rising and falling edges when daisy chaining

multiple devices.

Zero-Crossing Detection

The zero-crossing detection register enables the zero-

crossing detect feature. The zero-crossing detect fea-

ture reduces the audible noise (“clicks and pops”) that

result from wiper transitions. The wiper changes posi-

tion only when the voltage at L_ is the same as the volt-

age at H_. Each wiper has a zero-crossing and timeout

8 _______________________________________________________________________________________

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