MAX5134 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX5134 Datasheet PDF : 19 Pages
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Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
The MAX5134–MAX5137 digital inputs are double
buffered. Depending on the command issued through the
serial interface, the input register(s) can be loaded without
affecting the DAC register(s) using the write command. To
update the DAC registers, either pulse the LDAC input low
to synchronously update all DAC outputs, or use the soft-
ware LDAC command. Use the writethrough commands
(see Table 1) to update the DAC outputs immediately after
the data is received. Only use the writethrough command
to update the DAC output immediately.
The MAX5134/MAX5136 DAC code is unipolar binary
with VOUT_ = (code/65,536) x VREF. The MAX5135/
MAX5137 DAC code is unipolar binary with VOUT_ =
(code/4096) x VREF. See Table 1 for the serial interface
commands.
Connect the MAX5134–MAX5137 DVDD supply to the
supply of the host DSP or microprocessor. The AVDD
supply may be set to any voltage within the operating
range of 2.7V to 5.25V, but must be greater than or
equal to the DVDD supply.
Writing to the Devices
Write to the MAX5134–MAX5137 using the following
sequence:
1) Drive CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last),
observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the
internal register.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 33ns before the next transmis-
sion is started.
Figure 1 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
+5V
SCLK
SK
MAX5134– DIN
MAX5137
READY*
SO
MICROWIRE
PORT
SI*
CS
I/O
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES
*BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 2. Connections for MICROWIRE
READY*
SS
MISO*
MAX5134– DIN
MAX5137
SCLK
MOSI
SPI/QSPI
PORT
SCK
CS
I/O
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 3. Connections for SPI/QSPI
CS
DIN
SCLK
READY 1
READY 2
READY 3
SLAVE 1 DATA
SLAVE 2 DATA
SLAVE 3 DATA
1234
20 21 22 23 24 1 2 3 4 5
21 22 23 24 1 2 3 4 5
21 22 23 24
Figure 4. READY Timing
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