MAX5201AEUB-T Ver la hoja de datos (PDF) - Maxim Integrated

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MAX5201AEUB-T

Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in µMAX

Maxim Integrated 

Low-Cost, Voltage-Output, 16-Bit DACs with

Internal Reference in µMAX

ELECTRICAL CHARACTERISTICS—MAX5202/MAX5203

(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10kΩ in parallel with 250pF, TA = TMIN to TMAX, unless otherwise

noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

STATIC PERFORMANCE (Note 1)

Resolution

N

Integral Nonlinearity (Note 2)

INL

Differential Nonlinearity

(Note 2)

DNL

CONDITIONS

MAX520_AEUB

MAX520_ACUB

MAX520_BEUB

MAX520_A_UB (Note 3)

MAX520_BEUB (0°C to +105°C) (Note 3)

MAX520_BEUB (-40°C to 0°C)

MIN TYP MAX UNITS

16

Bits

±10 ±20

±10

±20

LSB

±20 ±40

±1

±1

LSB

±2

Offset Error

Inferred from measurement at 3800 hex and

FFFF hex

±3

±25

mV

Gain Error

Power-Supply Rejection

DYNAMIC PERFORMANCE

GE

Within DAC output range (Note 4)

PSR VDD = 3V ±10%, midscale input

±0.01

±0.06

±1.0

±0.5

%FSR

mV/V

DAC Output Range

Voltage-Output Slew Rate

(Note 2)

SR

0 to

V

VDD

0.6

V/µs

Output Settling Time

Output Noise

Reference Feedthrough

DAC Glitch Impulse

To ±1 LSB of FS,

VSTEP = 0.25 ✕ VREF to 0.75 ✕ VREF

Code = 8400 hex, 10kHz

Code = 0000 hex at 100kHz, VREF = 1VP-P

Major carry transition (code 7FFF hex to

code 8000 hex)

25

µs

175

nV/√Hz

1

mVP-P

10

nV⋅s

Digital Feedthrough

Code = 0000 hex; CS = VDD;

LDAC = 0; SCLK, DIN = 0 or VDD levels

10

nV⋅s

Wake-Up Time

From software shutdown to 90% of output

code = FFFF hex

50

µs

Power-Up Time

From power applied to 90% of output

code = FFFF hex

10

ms

4 _______________________________________________________________________________________

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