MAX5201AEUB-T Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX5201AEUB-T Datasheet PDF : 13 Pages
| |||
Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in µMAX
ELECTRICAL CHARACTERISTICS—MAX5200/MAX5201 (continued)
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10kΩ in parallel with 250pF, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
INTERNAL REFERENCE
VREF Output Voltage
TA = +25°C
VREF Tempco
TA = 0°C to +70°C
TA = -40°C to +105°C
DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
2.48
2.5
2.52
V
±15
ppm/°C
±20
Input High Voltage
VIH
2.4
V
Input Low Voltage
VIL
0.8
V
Input Hysteresis
VHYST
200
mV
Input Leakage
Input Capacitance
IIN
Digital inputs = 0 or VDD
CIN
±1
µA
15
pF
POWER REQUIREMENTS
Positive Power Supply
VDD
4.75
5.25
V
Positive Supply Current
IDD
All digital inputs at 0 or VDD (Note 5)
0.8
1.5
mA
Shutdown Supply Current
ISHDN All digital inputs at 0 or VDD
1
10
µA
TIMING CHARACTERISTICS
SCLK Frequency
SCLK Clock Period
fSCLK
tCP
10
MHz
100
ns
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
40
ns
40
ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
LDAC Pulse Width
CS Rise to LDAC Low Setup
SCLK Fall to CS Fall Ignore
CS Pulse Width Low for Shutdown
CS Pulse Width High
tDH
tCSS
tCSH
tCS0
tCS1
tLDAC
tLDACS
tCSOL
tCSWL
tCSWH
0
ns
40
ns
0
ns
10
ns
40
ns
40
ns
40
ns
10
ns
40
ns
100
ns
_______________________________________________________________________________________ 3
Share Link: 