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MAX519ACSE

2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs

Maxim Integrated 

2-Wire Serial 8-Bit DACs with

Rail-to-Rail Outputs

SDA

tSU, DAT

tLOW

tHD, DAT

tSU, STA

tHD, STA

tBUF

tSU, STO

SCL

tHD, STA

START CONDITION

tHIGH

tR

tF

REPEATED START CONDITION

STOP CONDITION START CONDITION

Figure 2. Two-Wire Serial Interface Timing Diagram

µC

SDA SCL

RC

1k

REF0

REF1

DUAL

DAC

MAX519

SCL

SDA

OUT0

AD0

OUT1

AD1

AD2

AD3

+1V

+4V

OFFSET ADJUSTMENT

GAIN ADJUSTMENT

DUAL

DAC

MAX518

SCL

SDA

OUT0

AD0

OUT1

AD1

BRIGHTNESS ADJUSTMENT

CONTRAST ADJUSTMENT

SINGLE REF0

+2.5V

DAC

SCL MAX517 OUT0

SDA

THRESHOLD ADJUSTMENT

+5V

AD0

AD1

Figure 3. MAX517/MAX518/MAX519 Application Circuit

The address byte and pairs of command and output

bytes are transmitted between the START and STOP con-

ditions. The SDA state is allowed to change only while

SCL is low, with the exception of START and STOP condi-

tions. SDA’s state is sampled, and therefore must remain

stable while SCL is high. Data is transmitted in 8-bit

bytes. Nine clock cycles are required to transfer the data

bits to the MAX517/MAX518/MAX519. Set SDA low dur-

ing the 9th clock cycle as the MAX517/MAX518/MAX519

pull SDA low during this time. RC (see Figure 3) limits the

current that flows during this time if SDA stays high for

short periods of time.

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a transmis-

sion with a START condition by transitioning SDA from

high to low while SCL is high (Figure 5). When the mas-

ter has finished communicating with the slave, it issues

a STOP condition by transitioning SDA from low to high

while SCL is high. The bus is then free for another

transmission.

The Slave Address

The MAX517/MAX518/MAX519 each have a 7-bit long

slave address (Figure 6). The first three bits (MSBs) of

the slave address have been factory programmed and

are always 010. In addition, the MAX517 and MAX518

have the next two bits factory programmed to 1s. The

logic state of the address inputs (AD0 and AD1 on the

MAX517/MAX518; AD0, AD1, AD2, and AD3 on the

MAX519) determine the LSB bits of the 7-bit slave

address. These input pins may be connected to VDD or

DGND, or they may be actively driven by TTL or CMOS

logic levels. The MAX517/MAX518 have four possible

slave addresses and therefore a maximum of four of

8 _______________________________________________________________________________________

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