0.9Ω, Low-Voltage, Single-Supply Quad SPST
Analog Switches
Test Circuits/Timing Diagrams
V+
V+ NO_
MAX4751
IN_
COM_
GND
VNO_
50Ω
VCOM_
35pF
VIH + 0.5V
IN_
0
VNO_
VCOM_
0
tR < 5ns
tF < 5ns
50%
50%
90%
tON
90%
tOFF
V+
VNC_
NC_ V+ NO_
VNO_
MAX4753
IN_
COM_
GND
50Ω
VCOM_
35pF
VIH + 0.5V
IN_
0
VNO_ or VNC_
VCOM_
0
90%
tBBM
tBBM = tON(NO_) - tOFF(NC_)
OR
tBBM = tON(NC_) - tOFF(NO_)
Figure1. Switching Times
90%
tBBM
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