MAX4719EBC Ver la hoja de datos (PDF) - Maxim Integrated
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MAX4719EBC Datasheet PDF : 11 Pages
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20Ω, 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-limited.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
Test Circuits/Timing Diagrams
MAX4719
VN_
NO_
OR NC_
LOGIC
INPUT
IN_
GND
V+
V+
COM_
RL
300Ω
VOUT
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 1. Switching Time
LOGIC VIH
INPUT VIL
50%
tr < 5ns
tf < 5ns
SWITCH 0V
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4719
VN_
LOGIC
INPUT
V+
V+
NC_
COM_
NO_
IN_
GND
VOUT
RL
300Ω
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
LOGIC VIH
INPUT
50%
VIL
VOUT
0.9 x VOUT
tBBM
8 _______________________________________________________________________________________
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