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MAX4736EUB

0.6Ω, Low-Voltage, Single-Supply, Dual SPDT Analog Switch

Maxim Integrated 

MAX4736

0.6Ω, Low-Voltage, Single-Supply, Dual SPDT

Analog Switch

Detailed Description

The MAX4736 is a low 0.8Ω max (at V+ = 2.7V) onresis-

tance, low-voltage, dual SPDT analog switch that oper-

ates from a 1.6V to 4.2V single supply. CMOS switch

construction allows switching analog signals that range

from GND to V+.

When powered from a 2.7V supply, the 0.8Ω max RON

allows high continuous currents to be switched in a variety

of applications.

Applications Information

Proper power-supply sequencing is recommended for all

CMOS devices. Do not exceed the absolute maximum

ratings; stresses beyond the listed ratings can cause per-

manent damage to the devices. Always sequence V+ on

first, followed by NO_, NC_, or COM_.

Although it is not required, power-supply bypassing

improves noise margin and prevents switching noise

propagation from the V+ supply to other components. A

0.1μF capacitor, connected from V+ to GND, is adequate

for most applications.

Logic Inputs

The MAX4736 logic inputs can be driven up to 3.6V,

regardless of the supply voltage. For example, with a 1.8V

supply, IN_ can be driven low to GND and high to 3.6V.

Driving IN_ rail-to-rail minimizes power consumption.

Analog Signal Levels

Analog signals that range over the entire supply voltage

(V+ to GND) can be passed with very little change in

onresistance (see Typical Operating Characteristics). The

switches are bidirectional, so the NO_, NC_, and COM_

pins can be used as either inputs or outputs.

Layout

High-speed switches require proper layout and design

procedures for optimum performance. Reduce stray induc-

tance and capacitance by keeping traces short and wide.

Ensure that bypass capacitors are as close to the device

as possible. Use large ground planes where possible.

Test Circuits/Timing Diagrams

MAX4736

VIN

LOGIC

INPUT

V+

NC_ or NO_

NO_ or NC_

V+

COM_

IN_

GND

VOUT

RL

CL

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

Figure 1. Switching Time

VIN_ = VIH + 0.5V

LOGIC

INPUT

0

SWITCH

OUTPUT

0

tr < 5ns

tf < 5ns

50%

tOFF

VOUT 0.9 x V0UT

0.9 x VOUT

tON

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

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