MAX3627 Ver la hoja de datos (PDF) - Maxim Integrated
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componentes Descripción
Fabricante
MAX3627 Datasheet PDF : 11 Pages
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+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at VDD, VDDA,
VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V
Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2,
Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7,
PLL_BP, FSELA, FSELB, OE, OSC_IN ...-0.3V to (VDD + 0.3V)
Voltage Range at X_IN ..........................................-0.3V to +1.2V
Voltage Range at X_OUT .................................-0.3V to (VDD - 0.6V)
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Power-Supply Current (Note 2)
PLL enabled
IDD
PLL bypassed
LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6)
Output High Voltage
VOH
Output Low Voltage
VOL
Differential Output Voltage
Amplitude
|VOD| Figure 1
Change in Magnitude of
Differential Output for
Complementary States
|VOD|
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for
Complementary States
VOS
|VOS|
Differential Output Impedance
Output Current
Shorted together
Short to ground (Note 3)
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
tr, tf
20% to 80%, RL = 100
PLL enabled
PLL bypassed (Note 4)
LVCMOS/LVTTL OUTPUT (Q7)
Output Frequency
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
VOH
IOH = -12mA
VOL
IOL = 12mA
tr, tf
20% to 80% at 125MHz (Note 5)
Output Duty-Cycle Distortion
PLL enabled
PLL bypassed (Note 4)
Output Impedance
ROUT
MIN TYP MAX UNITS
190 256
mA
175
0.925
250
1.475
V
V
400
mV
25
mV
1.125
1.275
V
25
mV
80
105 140
5
mA
8
100
200
330
ps
48
50
52
%
46
50
54
160
MHz
2.6
VDD
V
0.4
V
0.15
0.4
0.8
ns
46
50
54
%
45
50
55
15
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