MAX3094ECSE Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3094ECSE

±15kV ESD-Protected, 10Mbps, 3V/5V, Low-Power Quad RS-422/RS-485 Receivers

Maxim Integrated 

±15kV ESD-Protected, 10Mbps, 3V/5V,

Low-Power Quad RS-422/RS-485 Receivers

Typical Operating Characteristics (continued)

(VCC = +5V for MAX3093E, VCC = +3.3V for MAX3094E, TA = +25°C, unless otherwise noted.)

SHUTDOWN TIMING

MAX3093/94E TOC09

MAX3093E

Y VOLTAGE

5V/div

MAX3094E

Y VOLTAGE

G VOLTAGE

2V/div

2V/div

TIME (200ns/div)

CIRCUIT OF FIGURE 3,

S1 OPEN, S2 CLOSED, S3 = 1V

Pin Description

PIN NAME

FUNCTION

1

A-

Inverting Receiver A Input

2

A+

Noninverting Receiver A Input

Receiver A Output. Enabled when ENAC = high. YA will be logic high if A+ > A- by 200mV, and low if

3

YA

A+ < A- by 200mV. It will be logic high if A+ and A- remain floating. Otherwise, the state is undetermined.

YA goes high impedance when ENAC = low.

4

ENAC Receiver Output A and C Enable High. A logic high on this input enables receivers A and C.

5

YC

Receiver C Output. Same functionality as YA.

6

C+

Noninverting Receiver C Input

7

C-

Inverting Receiver C Input

8

GND Ground

9

D-

Inverting Receiver D Input

10

D+

Noninverting Receiver D Input

Receiver D Output. Enabled when ENBD = high. YD will be logic high if D+ > D- by 200mV, and low if

11

YD

D+ < D- by 200mV. It will be a logic high if D+ and D- remain floating. Otherwise, the state is undetermined.

YD goes high impedance when ENBD = low.

12

ENBD Receiver Output B and D Enable High. A logic high on this input enables receivers B and D.

13

YB

Receiver B Output. Same functionality as YD.

14

B+

Noninverting Receiver B Input

15

B-

Inverting Receiver B Input

16

VCC

Positive Supply

6 _______________________________________________________________________________________

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