MAX1664 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX1664 Datasheet PDF : 16 Pages
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Active-Matrix Liquid Crystal Display
(AMLCD) Supply
PHASE
PLLC
DETECTOR
CSHUNT
VCO
RPLLC
CPLLC
÷N*
÷2
DC-DC 1
÷4
DC-DC 2
BPCLK
*SEE TABLE 1 FOR
SELECTED VALUES OF N.
IN REF GND
Figure 2. Internal PLL Operation within the MAX1664
The heart of the PLL is the VCO, which is trimmed to a
nominal frequency of 1.92MHz for a control voltage (at
the PLLC pin) of 1.250V. This high-frequency internal
clock is divided digitally with a division ratio selected
by pin-strapping FPLL to GND, REF, or IN. This divided
clock is compared to the backplane clock by an inter-
nal phase comparator (rising-edge triggered). The
phase detector in turn adjusts the VCO control voltage
until the two frequencies (and phases) match. This
feedback loop is compensated at the PLLC pin.
In some applications, the backplane clock may be halt-
ed for several cycles between screen scans or may not
be immediately applied on power-up. The PLL contains
a proprietary phase-detector architecture that mini-
mizes frequency error during clock dropouts of more
than two cycles and re-establishes lock immediately
when the clock resumes.
Ready Indicator (RDY)
The RDY pin has an open-drain output and indicates
when all three outputs are in regulation. The open-drain
output becomes high impedance when all three convert-
er outputs are within 10% of their regulation setpoints.
Design Procedure and
______________Component Selection
Output Voltage Selection
The three output voltages as well as the DC bias for the
backplane clock are adjustable on the MAX1664, as
shown in Figure 3. Set each output using two standard
1% resistors to form a voltage divider between the
selected output and its respective feedback pin. Use
the following equations to calculate the resistances.
REF
R5
VOUT2+
R6
R7
VOUT2-
R8
MAX1664
FB2-
FB1
FB2+ BPDRV
VOUT1
R1
CFB1
CC
BPVDD
R2
R3
DC
BIAS
R4
Figure 3. Output Voltage Selection
BPVSS
DC-DC 1 Output
For VOUT1 = 5V, typical values are R2 = 100kΩ and R1
= 301kΩ. To set VOUT1 to another voltage, choose R2 =
100kΩ and CFB1 = 50pF, and calculate R1 as follows:
R1
=
R2
VOUT1
VFB1
- 1
DC-DC 2 Positive Output
For VOUT2+ = 15V, typical values are R8 = 49.9kΩ and
R7 = 549kΩ. To set VOUT2+ to another voltage, choose
R8 = 49.9kΩ and calculate R7 as follows:
R7
=
R8
VOUT2 +
VFB2 +
- 1
DC-DC 2 Negative Output
For the negative output voltage, the FB2- threshold volt-
age is 0. For VOUT2- = -5V, typical values are R5 =
49.9kΩ and R6 = 200kΩ. To set VOUT2+ to another volt-
age, choose R5 = 49.9kΩ and calculate R6 as follows:
R6 = R5 VOUT2-
VREF
DC Bias for the Backplane Driver
For VDCBIAS = VBPVDD/2, typical values are R3 = R4 =
100kΩ. To set the DC bias to a different value, choose
R4 and calculate R3 as follows:
R3
=
R4
VBPVDD
VDCBIAS
- VBPVSS
- VBPVSS
- 1
10 ______________________________________________________________________________________
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