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MAX1236

2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

Maxim Integrated 

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

TIMING CHARACTERISTICS (Figure 1) (continued)

(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =

4.096V (MAX1236/MAX1238), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

TA = +25°C, see Tables 1–5 for programming notation.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)

Serial Clock Frequency

fSCLH (Note 13)

1.7

MHz

Hold Time, Repeated START

Condition (Sr)

tHD, STA

160

ns

Low Period of the SCL Clock

High Period of the SCL Clock

tLOW

tHIGH

320

ns

120

ns

Setup Time for a Repeated START

Condition (Sr)

tSU, STA

160

ns

Data Hold Time

Data Setup Time

Rise Time of SCL Signal

(Current Source Enabled)

tHD, DAT (Note 10)

tSU, DAT

tRCL

0

150

ns

10

ns

20

80

ns

Rise Time of SCL Signal after

Acknowledge Bit

tRCL1 Measured from 0.3VDD - 0.7VDD

20

160

ns

Fall Time of SCL Signal

tFCL Measured from 0.3VDD - 0.7VDD

20

Rise Time of SDA Signal

tRDA Measured from 0.3VDD - 0.7VDD

20

Fall Time of SDA Signal

tFDA Measured from 0.3VDD - 0.7VDD (Note 11)

20

Setup Time for STOP (P) Condition tSU, STO

160

Capacitive Load for Each Bus Line CB

Pulse Width of Spike Suppressed

tSP (Notes 10 and 13)

0

80

ns

160

ns

160

ns

ns

400

pF

10

ns

Note 1: For DC accuracy, the MAX1236/MAX1238 are tested at VDD = 5V and the MAX1237/MAX1239 are tested at VDD = 3V. All

devices are configured for unipolar, single-ended inputs.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Note 3: Offset nulled.

Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion

time does not include acquisition time. SCL is the conversion clock in the external clock mode.

Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.

Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.

Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a

0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVP-P.

Note 9: Measured as for the MAX1237/MAX1239

[ ] ⎡

⎢ VFS(3.6V) − VFS(2.7V)

⎣⎢

×

2N

−

1⎤

⎥

VREF ⎦⎥

(3.6V − 2.7V)

_______________________________________________________________________________________ 5

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