M95256-BN3P Ver la hoja de datos (PDF) - STMicroelectronics

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M95256-BN3P

256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95256, M95128

SUMMARY DESCRIPTION

These electrically erasable programmable memo-

ry (EEPROM) devices are accessed by a high

speed SPI-compatible bus. The memory array is

organized as 32768 x 8 bit (M95256) and 16384 x

8 bit (M95128).

The device is accessed by a simple serial interface

that is SPI-compatible. The bus signals are C, D

and Q, as shown in Table 2. and Figure 2..

The device is selected when Chip Select (S) is tak-

en Low. Communications with the device can be

interrupted using Hold (HOLD).

Figure 2. Logic Diagram

VCC

D

C

S

W

HOLD

Q

M95xxx

VSS

AI01789C

Figure 3. DIP, SO and TSSOP Connections

M95xxx

S1

Q2

8 VCC

7 HOLD

W3

6C

VSS 4

5D

AI01790D

Note: See PACKAGE MECHANICAL section for package dimen-

sions, and how to identify pin-1.

Table 2. Signal Names

C

Serial Clock

D

Serial Data Input

Q

Serial Data Output

S

Chip Select

W

Write Protect

HOLD

Hold

VCC

Supply Voltage

VSS

Ground

5/39

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