M95160-X Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

M95160-X

16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock

STMicroelectronics 

Instructions

M95160-x, M95080-x

6.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

Register. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)

driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that

latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).

Otherwise, the Write Status Register (WRSR) instruction is not executed.

The instruction sequence is shown in Figure 10.

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-

timed write cycle that takes tW to complete (as specified in Table 21, Table 22, Table 23,

Table 24, Table 26 and Table 27).

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write

cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also

reset at the end of the write cycle tW.

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 and SRWD bits:

● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as

read only, as defined in Table 3.

● The SRWD bit (Status Register Write Disable bit), in accordance with the signal read

on the Write Protect pin (W), allows the user to set or reset the Write protection mode

of the Status Register itself, as defined in Table 6. When in Write-protected mode, the

Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the tW Write cycle.

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in

the Status Register. Bits b6, b5, b4 are always read as 0.

Table 6. Protection modes

W SRWD

signal bit

Mode

Write protection of the

Status Register

Memory content

Protected area(1) Unprotected area(1)

1

0

Status Register is

writable (if the WREN

0

1

0 Software- instruction has set the

protected WEL bit)

Write-protected

1

(SPM) The values in the BP1

and BP0 bits can be

Ready to accept

Write instructions

changed

Status Register is

0

Hardware- Hardware write-protected

1 protected The values in the BP1 Write-protected

(HPM) and BP0 bits cannot be

Ready to accept

Write instructions

changed

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.

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Doc ID 8028 Rev 10

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