M95160-X Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M95160-X

16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock

STMicroelectronics 

M95160-x, M95080-x

Instructions

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register (provided that the WEL bit has

previously been set by a WREN instruction), regardless of the logic level applied on the

Write Protect (W) input pin.

When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two

cases need to be considered, depending on the state of the Write Protect (W) input pin:

● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided

that the WEL bit has previously been set by a WREN instruction.

● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the WEL bit has previously been set by a WREN instruction. (Attempts to write to the

Status Register are rejected, and are not accepted for execution). As a consequence,

all the data bytes in the memory area, which are software-protected (SPM) by the Block

Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against

data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered by:

● either setting the SRWD bit after driving the Write Protect (W) input pin low

● or driving the Write Protect (W) input pin low after setting the SRWD bit

Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to

pull high the Write Protect (W) input pin.

If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode

(HPM) can never be activated, and only the Software-protected mode (SPM), using the

Block Protect (BP1, BP0) bits in the Status Register, can be used.

Table 7. Address range bits(1)

Device

Address bits

1. b15 to b11 are Don’t Care on the M95160-x.

b15 to b10 are Don’t Care on the M95080-x.

M95160-x

A10-A0

M95080-x

A9-A0

Figure 10. Write Status Register (WRSR) sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

Status

Register In

D

76543210

High Impedance

MSB

Q

AI02282D

Doc ID 8028 Rev 10

21/50

Share Link: