M95128-RM95128-MN6P Ver la hoja de datos (PDF) - STMicroelectronics

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M95128-RM95128-MN6P

128 Kbit Serial SPI bus EEPROM with high speed clock

STMicroelectronics 

Signal description

M95128, M95128-W, M95128-R

3.6

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either High or Low, and must be stable during all write instructions.

3.7

3.7.1

3.7.2

3.7.3

Supply voltage (VCC)

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

must be applied: this voltage must be a DC voltage within the specified [VCC(min),

VCC(max)] range, as defined in Table 7, Table 8 and Table 9. In order to secure a stable DC

supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually

of the order of 10nF to 100nF) close to the VCC/VSS package pins.

The VCC voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (tW).

Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip

Select (S) signal is not allowed to float and must follow the VCC voltage. The S line should

therefore be connected to VCC via a suitable pull-up resistor.

In addition, the Chip Select (S) input offers a built-in safety feature, as it is both edge

sensitive and level sensitive. Practically this means that after power-up, the device cannot

become selected until a falling edge has first been detected on Chip Select (S). So the Chip

Select (S) signal must first have been High and then gone Low before the first operation can

be started.

Internal device reset

In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)

circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any

instruction until the VCC has reached the Power On Reset threshold voltage (this threshold

is lower than the minimum VCC operating voltage defined in Section 9: DC and AC

parameters).

When VCC has passed the POR threshold voltage, the device is reset and in the following

state:

● in Standby Power mode

● deselected (at next Power-up, a falling edge is required on Chip Select (S) before any

instructions can be executed)

● not in the Hold Condition Status Register state:

– the Write Enable Latch (WEL) bit is reset to 0

– the Write In Progress (WIP) bit is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are at the same logic level as

when the device was last powered down (they are non-volatile bits).

10/41

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