M74HCT138M1R Ver la hoja de datos (PDF) - STMicroelectronics

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M74HCT138M1R

3 TO 8 LINE DECODER (INVERTING)

STMicroelectronics 

M74HCT138

3 TO 8 LINE DECODER (INVERTING)

s HIGH SPEED:

tPD = 16ns (TYP.) at VCC = 4.5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS :

VIH = 2V (MIN.) VIL = 0.8V (MAX)

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

DESCRIPTION

The M74HCT138 is an high speed CMOS 3 TO 8

LINE DECODER fabricated with silicon gate

C2MOS technology.

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

inhibited and all the 8 outputs go high. Three

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

TUBE

T&R

DIP

SOP

TSSOP

M74HCT138B1R

M74HCT138M1R M74HCT138RM13TR

M74HCT138TTR

enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/9

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