M61530FP Ver la hoja de datos (PDF) - Renesas Electronics

Número de pieza

componentes Descripción

Fabricante

M61530FP

4ch Electronic Volume with 5.1ch Analog Input

Renesas Electronics 

M61530FP

Relation between DATA and CLOCK

Latch condition

CLOCK

D0

D1

D2

D3

DATA

D13

D14

D15

The data signal is read on the rising edges of the CLOCK signal

The DATA line is driven high to latch

D0 to D15 at this time

1. Data transmission

The DATA signal is read on the rising edges of the CLOCK signal. The DATA line must always be low

on the falling edge of the CLOCK signal during transmission of the DATA signal.

2. Data Latch

Data for this IC is in 16-bits (D0 to D15) words. Latch the transmitted data by

driving the DATA line high on the falling edge of the CLOCK signal after the transmission of D15.

CLOCK and DATA timing

(D0 to D15)

t cr

(D15) L ATCH signal

DATA

75%

CLOCK 25%

tr

tSLD tHLD tSHD tHHD

t WHC

tf

t WLC

tSLD tHLD

Rev.1.0, Sep.19.2003, page 6 of 18

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