M5M5Y5672TG-25 Ver la hoja de datos (PDF) - Renesas Electronics

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Fabricante

M5M5Y5672TG-25

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Renesas Electronics 

MITSUBISHI LSIs

M5M5Y5672TG – 25,22,20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Special Function

Burst Cycles

The SRAM provides an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write

implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the

counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the

SRAM by driving the ADV pin low, into Load mode.

Burst Read

CLK

E1#

ADV

W#

BWx#

ADD

DQ

CQ

A

Read A

Q(A)

Q(A+1)

B

Q(A+2)

Q(A+3)

Burst Read

A+1

Burst Read

A+2

Burst Read

A+3

Read B

Burst Read

B+1

Burst Write

CLK

E1#

ADV

W#

BWx#

ADD

DQ

CQ

A

Write A

D(A)

D(A+1)

D(A+2)

B

D(A+3)

Burst Write

A+1

Burst Write

A+2

Burst Write

A+3

Burst Write

A

Write B

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Preliminary

M5M5Y5672TG REV.0.8

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