M5M5Y5636TG-20 Ver la hoja de datos (PDF) - Mitsumi

Número de pieza

componentes Descripción

Fabricante

M5M5Y5636TG-20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Mitsumi 

MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Pipelined Read Bank Switch with E1# Deselect

CLK

ADD

A

B

C

D

E

E1#

E2# Bank1

E2 Bank2

DQ

Bank1

CQ

Bank1

CQ Bank1

+ CQ Bank2

CQ

Bank2

DQ

Bank2

Q(A)

Q(B)

Q(C)

Note10. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously

deselected by E2 or E3 being sampled false.

In some applications it may be appropriate to pause between banks; to deselect both SRAMs with E1# before resuming read

operations. An E1# deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle

in the bank. Although the following drawing illustrates a E1# read pause upon switching from Bank 1 to Bank 2, a write to Bank 2

would have the same effect, causing the SRAM in Bank 2 to issue at least one clock before it is needed.

Output Driver Impedance Control

The ZQ pin of SRAMs supplied with selectable impedance drivers, allows selection between SRAM nominal drive strength

(ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications.

11

MITSUBISHI

Advanced Information

ELECTRIC

M5M5Y5636TG REV.0.0

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