M58WR128EB10ZB6T Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Fabricante
M58WR128EB10ZB6T
STMicroelectronics
M58WR128EB10ZB6T Datasheet PDF : 87 Pages
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M58WR128ET, M58WR128EB
REVISION HISTORY
Table 48. Document Revision History
Date
Version
Revision Details
06-Sep-2002
1.0
First Issue
19-Dec-2002
Device Codes changed. VFBGA60 Package defined. 85ns Speed Class removed,
80ns Speed Class added. 70ns Speed Class characterized (certain timings
modified). Command Interface description of invalid combinations clarified.
Descriptions clarified: Clear Status Register Command, Program/Erase Suspend
1.1
Command, Set Configuration Register Command, Factory Program Commands,
WAIT signal’s behavior.
Tables 5, 7, 9 and 10 corrected. Notes to Figures 12, 13 and 14 modified. Flowcharts
and Pseudo Code revised. CFI, Device Geometry Definition table address offsets
35h, 38h reserved. Revision History moved to end of document.
21-May-2003
Automatic Standby mode explained under Asynchronous Read Mode. Minor text
changes in Clear Status Register Command, Quadruple Enhanced Factory Program
Command and Synchronous Burst Read Mode.
Bank Erase Command moved from the Standard to the Factory Program
Commands. Number of Bank Erase cycles limited to 100. Erase replaced by Block
Erase in Tables 11 and 12, Dual Operations Allowed in Other Banks and the Same
Bank, respectively.
1.2
IPP2 parameter for VPP = VPPH removed from Table 18, DC Characteristics -
Currents. Several cross-references corrected.
VDDQ range split into two in Tables 20 and 21, Asynchronous and Synchronous Read
AC Characteristics: for VDDQ = 2.2V to 3.3V, tAVQV1, tELTV, tEHTZ, tEHQZ, tGLQV, tAVLH,
tELLH and tLLLH in Table 20 and all the timings in Table 21 were modified.
Daisy chain information added (see Figures 20 and 21 and Table 27).
Table 30, M58WR128ET - Block Addresses in Main Banks, corrected. CFI
information corrected at offset (P+15)h = 4Eh in Table 40, and at offset (P+38)h =
71h in Table 43.
86/87
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