M58BF008ZA Ver la hoja de datos (PDF) - STMicroelectronics
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M58BF008ZA Datasheet PDF : 36 Pages
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M58BF008
Table 7. Instructions
Mne-
monic
Instruction
RD
RSR
CLRS
RSIG
EE
OBEE
Read Memory
Array
Read Status
Register
Clear Status
Register
Read Electronic
Signature
Erase
Overlay Block
Erase
Cycles
1st Cycle
Operation Address
1+
Write
00000h
1+
Write
00000h
1
Write
00000h
1+++
2
2
Write
Write
Write
00000h
00000h
00000h
PG
Program
2
Write
00000h
OBPG
Overlay Block
Program
2
PES
Program/Erase
Suspend
1
PER
Program/Erase
Resume
1
ART
Asynch/Synch
Read Toggle
1
WBT
Wrap//No-wrap
Burst Toggle
1
Overlay Block
OBT
Read En/Dis
1+
Toggle
Write
00000h
Write
Write
Write
Write
00000h
00000h
00000h
00000h
Write
00000h
Data
Operation
2nd Cycle
Addre ss.
Data
FFh
Read Read Address Data Output
70h
Read
X
Status
Register
50h
90h
Read
Signature
Address
Electronic
Signature
20h
Write Block Address
D0h
02h
Write
Overlay Block
Address
0Dh
40h
Write
Program
Address
Data Input
Overlay Block
04h
Write
Program
Data Input
Address
B0h
D0h
60h
30h
06h
Read Read Address Data Output
Read Memory Array (RD). The Read Memory
Array instruction consists of one write cycle giving
the command FFh at the address 00000h. Subse-
quent read operations will read the addressed lo-
cation and output the memory data. The data can
be read from the Main memory Array or the Over-
lay memory block if it is enabled.
Read Status Register (RSR). The Read Status
Register instruction consists of one write cycle giv-
ing the command 70h at the address 00000h. Sub-
sequent read operations will output the Status
Register contents. See Table 8 for an explanation
of the Status Register bits. The Status Register in-
dicates when a program or Erase operation is
complete and its success or failure. The Status
Register also indicates if the Overlay block is ac-
cessible for reading. The Read Status Register in-
struction may be given at any time, including while
a program or erase operation in progress.
Clear Status Register (CLRS). The Clear Status
Register instruction consists of one write cycle giv-
ing the command 50h at the address 00000h. The
Clear Status Register command clears the bits 3,
4 and 5 of the Status Register if they have been set
to ’1’ by the P/E.C. operation. The Clear Status
Register command should be given after an error
has been detected and before any new operation
is attempted. A Read Memory Array command
should also be given before data can be read from
the memory array.
Read Electronic Signature (RSIG). The Read
Electronic Signature instruction consists of a first
write cycle giving the command 90h at the address
00000h. This is followed by three read operations
at addresses xxxx0h, xxxx1h and xxxx2h which
output the manufacturer, device and version
codes respectively.
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