M5481 Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

M5481

LED DISPLAY DRIVER

STMicroelectronics 

M5481

Figure 4. Input Data Format

CLOCK

DATA

1

START BIT 1

36

BIT 34 BIT 35

LOAD

(INTERNAL)

RESET

(INTERNAL)

At the low state of the clock a RESET signal is

generated which clears all the shift registers for

the next set of data. The shift registers are static

master slave configurations. There is no clear for

the master portion of the first shift register, thus al-

lowing continuous operation.

There must be a complete set of 36 clocks or

the shift registers will not clear.

When power is first applied to the chip an internal

power ON reset signal is generated which resets

all registers and all latches. The START bit and the

first clock reset the chip to its normal operation.

Figure 5 shows the timing relationships between

Data, Clock and DATA ENABLE.

A maximum clock frequency of 0.5MHz is as-

sumed.

Table 3 shows the Output Data Format for the

M5481. Because it uses only 14 of the possible

outputs, 21 of the bits (including bit 35 which was

already unused in the M5450) are “Don’t Cares” .

For applications where a lesser number of outputs

are used it is possible to either increase the cur-

rent per output or operate the part at higher than

1V Vout.

The following equation can be used for calcula-

tions.

Tj = [(Vout) (ILED) (No. of segments) + VDD x 7mA]

x (80°C/W) + Tamb

where:

Tj = junction temperature (150°Cmax)

Vout = voltage at the LED driver outputs

ILED = LED current

80°C/W = thermal coefficient of the package

Tamb = ambiant temperature

Figure 5.

CLOCK

DATA

DATA ENABLE

300ns (min.)

100ns (min.)

Table 3. Serial Data Bus / Outputs Correspondance

5451 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 START

5481 X X X X X 14 13 X X X X 12 11 10 9 X X X START

5450 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 START

5481 X 8 7 6 5 X X X X 4 3 2 1 X X X X START

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