M48Z512BV Ver la hoja de datos (PDF) - STMicroelectronics
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M48Z512BV Datasheet PDF : 20 Pages
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M48Z512BV
Operating modes
Table 3. READ mode AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
tAVAV READ cycle time
85
ns
tAVQV Address valid to output valid
85
ns
tELQV Chip enable low to output valid
85
ns
tGLQV
tELQX(2)
tGLQX(2)
tEHQZ(2)
tGHQZ(2)
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
45
ns
5
ns
5
ns
35
ns
25
ns
tAXQX Address transition to output transition
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
2.2
WRITE mode
The M48Z512BV is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for a
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
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