M48Z2M1Y(2003) Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M48Z2M1Y
(Rev.:2003)

5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z2M1Y, M48Z2M1V

WRITE Mode

The M48Z2M1Y/V is in the WRITE Mode whenev-

er W and E are active. The start of a WRITE is ref-

erenced from the latter occurring falling edge of W

or E. A WRITE is terminated by the earlier rising

edge of W or E.

The addresses must be held valid throughout the

cycle. E or W must return high for minimum of tE-

HAX from E or tWHAX from W prior to the initiation

of another READ or WRITE cycle. Data-in must be

valid tDVEH or tDVWH prior to the end of WRITE and

remain valid for tEHDX or tWHDX afterward. G

should be kept high during WRITE cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G, a low on W

will disable the outputs tWLQZ after W falls.

Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms

A0-A20

E

W

DQ0-DQ7

Note: Output Enable (G) = High.

tAVEL

tAVAV

VALID

tAVWH

tWHAX

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI02053

Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms

A0-A20

E

tAVEL

tAVWL

tAVAV

VALID

tAVEH

tELEH

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

Note: Output Enable (G) = High.

tDVEH

AI02054

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