M34D64-WDW6T Ver la hoja de datos (PDF) - STMicroelectronics

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M34D64-WDW6T

64 Kbit Serial I²C Bus EEPROM With Hardware Write Control on Top Quarter of Memory

STMicroelectronics 

M34D64

Figure 9. Read Mode Sequences

CURRENT

ADDRESS

READ

ACK

NO ACK

DEV SEL

DATA OUT

R/W

RANDOM

ADDRESS

READ

ACK

ACK

ACK

ACK

NO ACK

DEV SEL *

BYTE ADDR BYTE ADDR

DEV SEL *

DATA OUT

R/W

R/W

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

ACK

ACK

DEV SEL

DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

ACK

ACK

ACK

ACK

ACK

DEV SEL *

BYTE ADDR BYTE ADDR

DEV SEL *

DATA OUT 1

R/W

R/W

ACK

NO ACK

DATA OUT N

AI01105C

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

must not acknowledge the byte, and terminates

Read Operations

the transfer with a Stop condition.

Read operations are performed independently of

the state of the Write Control (WC) signal.

Random Address Read

A dummy Write is performed to load the address

into the address counter (as shown in Figure 9) but

without sending a Stop condition. Then, the bus

master sends another Start condition, and repeats

the Device Select Code, with the RW bit set to 1.

The device acknowledges this, and outputs the

contents of the addressed byte. The bus master

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read operation, following a Start

condition, the bus master only sends a Device

Select Code with the RW bit set to 1. The device

acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The bus master

terminates the transfer with a Stop condition, as

shown in Figure 9, without acknowledging the

byte.

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