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M34C02-RBN1

2 Kbit Serial I²C Bus EEPROM For DIMM Serial Presence Detect

STMicroelectronics 

M34C02

SUMMARY DESCRIPTION

The M34C02 is a 2 Kbit serial EEPROM memory

able to lock permanently the data in its first half

(from location 00h to 7Fh). This facility has been

designed specifically for use in DRAM DIMMs

(dual interline memory modules) with Serial

Presence Detect. All the information concerning

the DRAM module configuration (such as its

access speed, its size, its organization) can be

kept write protected in the first half of the memory.

This bottom half of the memory area can be write-

protected using a specially designed software

write protection mechanism. By sending the

device a specific sequence, the first 128 bytes of

the memory become permanently write protected.

Care must be taken when using this sequence as

its effect cannot be reversed. In addition, the

device allows the entire memory area to be write

protected, using the WC input (for example by

tieing this input to VCC).

These I2C-compatible electrically erasable

programmable memory (EEPROM) devices are

organized as 256x8 bits.

Figure 2. Logic Diagram

VCC

3

E0-E2

SCL

WC

M34C02

SDA

VSS

AI01931

I2C uses a two wire serial interface, comprising a

bi-directional data line and a clock line. The device

carries a built-in 4-bit Device Type Identifier code

(1010) in accordance with the I2C bus definition to

access the memory area and a second Device

Type Identifier Code (0110) to access the

Protection Register. These codes are used

together with three chip enable inputs (E2, E1, E0)

so that up to eight 2 Kbit devices may be attached

to the I²C bus and selected individually.

The device behaves as a slave device in the I2C

protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are

initiated by a START condition, generated by the

bus master. The START condition is followed by a

Device Select Code and RW bit (as described in

Table 2), terminated by an acknowledge bit.

When writing data to the memory, the memory

inserts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and

after a NoAck for READ.

Figure 3. DIP, SO, TSSOP and VFDFPN

Connections (Top View)

M34C02

E0 1

E1 2

8 VCC

7 WC

E2 3

6 SCL

VSS 4

5 SDA

AI01932C

Note: 1. See the pages after page 19 for package dimensions,

and how to identify pin-1.

Table 1. Signal Names

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

VCC

VSS

Supply Voltage

Ground

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent

Write operations during power up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until VCC has reached the POR

threshold value, and all operations are disabled –

the device will not respond to any command. In the

same way, when VCC drops from the operating

voltage, below the POR threshold value, all

operations are disabled and the device will not

respond to any command.

A stable and valid VCC (as defined in Tables 6 to

9) must be applied before applying any logic

signal.

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