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M34C02-RBN1

2 Kbit Serial I²C Bus EEPROM For DIMM Serial Presence Detect

STMicroelectronics 

M34C02

Sequential Read

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 10.

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, for an acknowledgment during the

9th bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device termi-

nates the data transfer and switches to its Stand-

by mode.

USE WITHIN A DRAM DIMM

In the application, the M34C02 is soldered directly

in the printed circuit module. The 3 Chip Enable

inputs (pins 1, 2 and 3) are wired at VCC or VSS

through the DIMM socket (see Table 4). The pull-

up resistors needed for normal behavior of the I2C

bus are connected on the I2C bus of the mother-

board (as shown in Figure 11).

The Write Control (WC) of the M34C02 can be left

unconnected. However, connecting it to VSS is

recommended, to maintain full read and write

access.

Programming the M34C02

When the M34C02 is delivered, full read and write

access is given to the whole memory array. It is

recommended that the first step is to use the test

equipment to write the module information (such

as its access speed, its size, its organization) to

the first half of the memory, starting from the first

memory location. When the data has been

validated, the test equipment can send a Write

command to the Protection Register, using the

device select code ’01100000b’ followed by an

address and data byte (made up of Don’t Care

values) as shown in Figure 6. The first 128 bytes

of the memory area are then write-protected, and

the M34C02 will no longer respond to the specific

device select code ’0110000xb’. It is not possible

to reverse this sequence.

Table 4. DRAM DIMM Connections

DIMM Position

E2

E1

E0

0

VSS

VSS

VSS

1

VSS

VSS

VCC

2

VSS

VCC

VSS

3

VSS

VCC

VCC

4

VCC

VSS

VSS

5

VCC

VSS

VCC

6

VCC

VCC

VSS

7

VCC

VCC

VCC

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh).

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