M34C02(1999) Ver la hoja de datos (PDF) - STMicroelectronics
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M34C02 Datasheet PDF : 19 Pages
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M34C02
Figure 5. How to Set the Write Protection
Memory
Area
FFh
Standard
Array
80h
7Fh
Standard
Array
00h
Default EEPROM memory area
state before write access
to the Protect Register
FFh
Standard
Array
80h
7Fh
Write
Protected
Array
00h
State of the EEPROM memory
area after write access
to the Protect Register
AI01936C
Figure 6. Write Mode Sequences in the Non Write-Protected Area
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
PAGE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
R/W
ACK
ACK
DATA IN N
AI01941
significant bits only) is incremented. The transfer is
terminated by the master generating a STOP
condition.
When the master generates a STOP condition
immediately after the Ack bit (in the “10th bit†time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (tw) is shown in Table 9,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the
master.
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