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4250

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(6) Control register related to interrupt

• Timer control register V1

Interrupt enable bits of external and timer 1 are assigned

to register V1. Set the contents of this register through

register A with the TV1A instruction. The TAV1 instruction

can be used to transfer the contents of register V1 to register

A.

Table 6 Control register related to interrupt

Timer control register V1

at reset : 00002

at RAM back-up : 00002

R/W

V13 G1/TOUT pin function selection bit

0 Port G1 (I/O)

1 TOUT pin (output)/port G1(input)

V12 Prescaler/timer 1 operation start bit

0 Prescaler stop (initial state) / timer 1 stop (state retained)

1 Prescaler / timer 1 operation

V11 Timer 1 interrupt enable bit

0 Interrupt disabled (SNZ1 instruction is valid)

1 Interrupt enabled (SNZ1 instruction is invalid)

V10 External interrupt enable bit

0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid)

Note: “R” represents read enabled, and “W” represents write enabled.

(7) Interrupt sequence

Interrupts occur only when the respective INTE flag, interrupt

enable bits (V10, V11), and interrupt request flags (EXF0, T1F)

are “1.” The interrupt actually occurs 2 to 3 machine cycles

after the cycle in which all three conditions are satisfied. The

interrupt occurs after 3 machine cycles only when the three

interrupt conditions are satisfied on execution of other than

one-cycle instructions (Refer to Figure 16).

q When an interrupt request flag is set after its interrupt is enabled

f (XIN)

1 machine cycle

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

Interrupt enable

flag (INTE)

EI instruction

execution cycle

Interrupt enabled state.

T1 T2 T3 T4

Interrupt disabled state.

External

interrupt

G0/INT pin

EXF0 flag

Retaining level for 5 cycles or more

of f(XIN) is necessary.

Interrupt activated

condition is satisfied.

Timer 1

interrupt

T1F flag

Flag cleared

2 to 3 machine cycles

(Notes 1, 2)

Software starts from

the interrupt address.

Notes 1: The address is stacked to the last cycle.

2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Fig. 16 Interrupt sequence

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ELECTRIC

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