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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to an

individual address (interrupt address) according to each in-

terrupt source. An interrupt occurs when the following 3

conditions are satisfied.

• An interrupt activated condition is satisfied

(request flag = “1”)

• Interrupt enable bit = “1”

(interrupt request occurrence enabled)

• Interrupt enable flag (INTE) = “1” (interrupt enabled)

Table 3 shows interrupt sources. (Refer to each interrupt

request flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the

every interrupt enable/disable. Interrupts are enabled

when INTE flag is set to “1” with the EI instruction and

disabled when INTE flag is cleared to “0” with the DI

instruction. When any interrupt occurs, the INTE flag is

automatically cleared to “0,” so that other interrupts

are disabled until the EI instruction is executed.

(2) Interrupt enable bit (V10, V11)

Use an interrupt enable bit of interrupt control register

V1 to select the corresponding interrupt or skip instruc-

tion.

Table 4 shows the interrupt request flag, interrupt en-

able bit and skip instruction.

Table 5 shows the interrupt enable bit function.

Table 3 Interrupt sources

Priority

Interrupt name Activated condition

level

1 External interrupt Level change of INT

pin

2 Timer 1 interrupt Timer 1 underflow

Interrupt

address

Address 0

in page 1

Address 2

in page 1

Table 4 Interrupt request flag, interrupt enable bit and

skip instruction

Interrupt name Request flag Enable bit Skip instruction

External interrupt EXF0

V10

SNZ0

Timer 1 interrupt

T1F

V11

SNZ1

Table 5 Interrupt enable bit function

Interrupt enable bit

Occurrence of

interrupt request

1

Enabled

0

Disabled

Skip instruction

Invalid

Valid

(3) Interrupt request flag

When the activated condition for each interrupt is sat-

isfied, the corresponding interrupt request flag is set to

“1.” Each interrupt request flag is cleared to “0” when

either;

• an interrupt occurs, or

• the next instruction is skipped with a skip instruc-

tion.

Each interrupt request flag is set when the activated

condition is satisfied even if the interrupt is disabled

by the INTE flag or its interrupt enable bit. Once set,

the interrupt request flag retains set until a clear con-

dition is satisfied.

Accordingly, an interrupt occurs when the interrupt dis-

able state is released while the interrupt request flag

is set.

If more than one interrupt request flag is set when the

interrupt disable state is released, the interrupt priority

level is as follows shown in Table 3.

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