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M2V28S20TP

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Jun. '99

MITSUBISHI LSIs

M2V28S20TP-6,-7,-8

M2V28S30TP-6,-7,-7L,-8,-8L

M2V28S40TP-7,-7L,-8,-8L

128M Synchronous DRAM

(4-BANK x 8,388,608-WORD x 4-BIT)

(4-BANK x 4,194,304-WORD x 8-BIT)

(4-BANK x 2,097,152-WORD x 16-BIT)

[ Read Interrupted by Precharge ]

Burst read operation can be interrupted by precharge of the same bank . READ to PRE

interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS

Latency. As a result, READ to PRE interval determines valid data length to be output. The figure

below shows examples of BL=4.

Read Interrupted by Precharge (BL=4)

CLK

CL=3

Command

DQ

Command

DQ

Command

DQ

READ

READ

PRE

Q0 Q1 Q2

PRE

Q0 Q1

READ PRE

Q0

CL=2

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

MITSUBISHI ELECTRIC

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