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M2S56D20TP

256M Double Data Rate Synchronous DRAM

Mitsumi 

DDR SDRAM (Rev.0.0)

Sep.'99 Preliminary

MITSUBISHI LSIs

M2S56D20/ 30 TP

256M Double Data Rate Synchronous DRAM

PIN FUNCTION

SYMBOL

CLK,/CLK

CKE

TYPE

Input

Input

DESCRIPTION

Clock: CLK and /CLK are differential clock inputs. All address and control

input signals are sampled on the crossing of the positive edge of CLK and

negative edge of /CLK. Output (read) data is referenced to the crossings of

CLK and /CLK (both directions of crossing).

Clock Enable: CKE controls internal clock. When CKE is low, internal clock

for the following cycle is ceased. CKE is also used to select auto / self

refresh. After self refresh mode is started, CKE becomes asynchronous

input. Self refresh is maintained as long as CKE is low.

/CS

Input

Chip Select: When /CS is high, any command means No Operation.

/RAS, /CAS, /WE

A0-12

BA0,1

DQ0-7(x8),

DQ0-3(x4)

DQS

/QFC

DM

Vdd, Vss

Input

Input

Input

Input / Output

Input / Output

Output

Input

Power Supply

Combination of /RAS, /CAS, /WE defines basic commands.

A0-12 specify the Row / Column Address in conjunction with BA0,1. The

Row Address is specified by A0-12. The Column Address is specified by

A0-9,11(x4) and A0-9(x8). A10 is also used to indicate precharge option.

When A10 is high at a read / write command, an auto precharge is

performed. When A10 is high at a precharge command, all banks are

precharged.

Bank Address: BA0,1 specifies one of four banks to which a command is

applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.

Data Input/Output: Data bus

Data Strobe: Output with read data, input with write data. Edge-aligned

with read data, centered in write data. Used to capture write data.

FET Control: Optional. Output during every Read and Write access. Can

be used to control

isolation switches on modules. Open drain output.

Input Data Mask: DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH along with that input data during a

WRITE access. DM is sampled on both edges of DQS. Although DM pins

are input only, the DM loading matches the DQ and DQS loading.

Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ

Vref

Power Supply VddQ and VssQ are supplied to the Output Buffers only.

Input

SSTL_2 reference voltage.

MITSUBISHI

ELECTRIC

4

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