M2S56D20TP Ver la hoja de datos (PDF) - Mitsumi

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componentes Descripción

Fabricante

M2S56D20TP

256M Double Data Rate Synchronous DRAM

Mitsumi 

DDR SDRAM (Rev.0.0)

Sep.'99 Preliminary

BLOCK DIAGRAM

DLL

MITSUBISHI LSIs

M2S56D20/ 30 TP

256M Double Data Rate Synchronous DRAM

DQ0 - 7

/QFC DQS

I/O Buffer

QFC&QS Buffer

Memory

Array

Bank #0

Memory

Array

Bank #1

Memory

Array

Bank #2

Memory

Array

Bank #3

Mode Register

Control Circuitry

Address Buffer

A0-12 BA0,1

Clock Buffer

CLK,/CLK CKE

Control Signal Buffer

/CS /RAS /CAS /WE DM

Type Designation Code

M 2 S 56 D 3 0

This rule is applied to only Synchronous DRAM family.

TP -

Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0

75: 133MHz@CL=2.5,100MHz@CL=2.0

Package Type TP: TSOP(II)

Process Generation

Function Reserved for Future Use

Organization 2n 2: x4, 3: x8

DDR Synchronous DRAM

Density 56: 256M bits

Interface V:LVTTL, S:SSTL_3, _2

Memory Style (DRAM)

Mitsubishi Main Designation

MITSUBISHI

ELECTRIC

3

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