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M28W800C-ZBT

8 Mbit (512Kb x16, Boot Block) 3V Supply Flash Memory

STMicroelectronics 

M28W800CT, M28W800CB

SUMMARY DESCRIPTION

The M28W800C is a 8 Mbit (512Kbit x 16) non-vol-

atile Flash memory that can be erased electrically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 to 3.6V)

supply. VDDQ allows to drive the I/O pin down to

1.65V. An optional 12V VPP power supply is pro-

vided to speed up customer programming.

The device features an asymmetrical blocked ar-

chitecture. The M28W800C has an array of 23

blocks: 8 Parameter Blocks of 4 KWord and 15

Main Blocks of 32 KWord. M28W800CT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W800CB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

The M28W800C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When VPP ≤ VPPLK all blocks are protected against

program or erase. All blocks are locked at power-

up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system design. The Protection Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by ST, while the

second one is one-time-programmable by the us-

er. The user programmable segment can be per-

manently protected. The Security Block,

parameter block 0, can be permanently protected

by the user. Figure 6, shows the Security Block

and Protection Register Memory Map.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm)

and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram

VDD VDDQ VPP

19

A0-A18

16

DQ0-DQ15

W

E

M28W800CT

G

M28W800CB

RP

WP

VSS

AI03806

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ15 Data Input/Output

E

Chip Enable

G

Output Enable

W

Write Enable

RP

Reset

WP

Write Protect

VDD

Core Power Supply

VDDQ

Power Supply for

Input/Output

VPP

Optional Supply Voltage for

Fast Program & Erase

VSS

Ground

NC

Not Connected Internally

5/49

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