EDE5104GBSA Ver la hoja de datos (PDF) - Elpida Memory, Inc

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componentes Descripción

Fabricante

EDE5104GBSA

512M bits DDR-II SDRAM

Elpida Memory, Inc 

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

max.

Parameter

Symbol Grade × 4, × 8 × 16

Unit Test condition

Operating current

(ACT-PRE)

IDD0

TBD

one bank; tRC = tRC (min.) ; tCK = tCK (min.) ; DQ,

TBD

mA

DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock

cycle

Operating current

(ACT-READ-PRE)

IDD1

TBD

one bank; Burst = 4; tRC = tRC (min.) ;

TBD

mA

CL = 4; tCK = tCK (min.) ; IOUT = 0mA;

address and control inputs changing once per clock

cycle

Precharge power-down

standby current

IDD2P

TBD

TBD

mA

all banks idle; power-down mode; CKE = VIL (max.);

tCK = tCK (min.)

Idle standby current IDD2N

TBD

/CS = VIH (min.); all banks idle; CKE = VIH (min.);

TBD mA tCK = tCK (min.) ; address and control inputs

changing once per clock cycle

Active power-down

standby current

IDD3P

TBD

one bank active; power-down mode; CKE = VIL

TBD mA (max.);

tCK = tCK (min.)

Active standby current IDD3N

TBD

one bank; active;/CS = VIH (min.);

CKE = VIH (min.); tRC = tRAS max; tCK = tCK

TBD mA (min.); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing

once per clock cycle

Operating current

IDD4R

(Burst read operating)

TBD

one bank; Burst = 4; burst; address and control

TBD

mA

inputs changing once per clock cycle; DQ and DQS

outputs changing twice per clock cycle; CL = 4; tCK

= tCK (min.) ; IOUT = 0mA

Operating current

(Burst write operating) IDD4W

TBD

one bank; Burst = 4; writes; continuous burst;

address and control inputs changing once per clock

TBD mA cycle; DQ and DQS inputs changing twice per clock

cycle; CL = 4;

tCK = tCK (min.)

Auto-refresh current IDD5

TBD

TBD mA tRC = tRFC (min.)

Self-refresh current IDD6

TBD

TBD mA Self Refresh Mode; CKE = 0.2V

Operating current

(Bank interleaving)

IDD7

TBD

Four bank interleaving READs (BL4) with auto

TBD

mA

precharge, tRC = tRC (min.); Address and control

inputs change during Active, READ, or WRITE

commands.

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

Unit

Minimum required output pull-up under AC

test load

VOH

VTT + 0.603

V

Maximum required output pull-down under

AC test load

VOL

VTT – 0.603

V

Output timing measurement reference level VOTR

0.5 × VDDQ

V

Output minimum sink DC current

IOL

+13.4

mA

Output minimum source DC current

IOH

–13.4

mA

Note: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.7V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

5. After OCD calibration to 18Ω at TA = 25°C, VDD = VDDQ = 1.8V.

Notes

5

5

1

3, 4, 5

2, 4, 5

Preliminary Data Sheet E0249E30 (Ver. 3.0)

6

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