M28F420 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M28F420

4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

STMicroelectronics 

M28F410, M28F420

Table 8. AC Measurement Conditions

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

SRAM Interface Levels

≤ 10ns

0 to 3V

1.5V

EPROM Interface Levels

≤ 10ns

0.45V to 2.4V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

SRAM Interface

3V

0V

EPROM Interface

2.4V

0.45V

1.5V

2.0V

0.8V

AI01275

Figure 4. AC Testing Load Circuit

1.3V

1N914

DEVICE

UNDER

TEST

3.3kΩ

OUT

CL = 30pF or 100pF

CL = 30pF for SRAM Interface

CL = 100pF for EPROM Interface

CL includes JIG capacitance

AI01276

Table 9. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol

Parameter

Test Condition

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

Note: 1. Sampled only, not 100% tested.

VOUT = 0V

Min

Max

Unit

6

pF

12

pF

DEVICE OPERATION

Signal Descriptions

A0-A17 Address Inputs. The address signals,

inputs for the memory array, are latched during a

write operation.

A9 Address Input is also used for the Electronic

Signature Operation. When A9 is raised to 12V the

Electronic Signature may be read. The A0 signal is

used to read two words or bytes, when A0 is Low

the Manufacturercode is read and when A0 is High

the Device code. When BYTE is Low DQ0-DQ7

output the codes and DQ8-DQ15 are don’t care,

when BYTE is High DQ0-DQ7 output the codes

and DQ8-DQ15 output 00h.

DQ0-DQ7 Data Input/Outputs. The data inputs, a

byte or the lower byte of a word to be programmed

or a command to the C.I., are latched when both

Chip Enable E and Write Enable W are active. The

data output from the memory Array, the Electronic

Signature or Status Register is valid when Chip

Enable E and Output Enable G are active. The

output is high impedance when the chip is dese-

lected or the outputs are disabled.

DQ8-DQ14 and DQ15A-1 Data Input/Outputs.

These input/outputs are used in the word-wide

organization. When BYTE is High for the most

significant byte of the input or output, functioning

as described for DQ0-DQ7 above. When BYTE is

Low, DQ8-DQ14 are high impedance, DQ15A-1 is

the Address A-1 input.

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