M28F420 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M28F420

4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

STMicroelectronics 

M28F410, M28F420

Table 3. Operations

Operation

E

G

W

RP BYTE DQ0 - DQ7 DQ8 - DQ14

DQ15A-1

Read Word

VIL

VIL

VIH

VIH

VIH Data Output Data Output

Data Output

Read Byte

VIL

VIL

VIH

VIH

VIL

Data Output

Hi-Z

Address Input

Write Word

VIL

VIH

VIL

VIH

VIH

Data Input

Data Input

Data Input

Write Byte

VIL

VIH

VIL

VIH

VIL

Data Input

Hi-Z

Address Input

Output Disable

VIL

VIH

VIH

VIH

X

Hi-Z

Hi-Z

Hi-Z

Standby

VIH

X

X

VIH

X

Hi-Z

Hi-Z

Hi-Z

Power Down

X

X

X

VIL

X

Hi-Z

Hi-Z

Hi-Z

Note: X = VIL or VIH, VPP = VPPL or VPPH

Table 4. Electronic Signature

Organi-

sation

Code

Device

E

G

W

BYTE

A0

A9

A1-A8 &

A10-A17

Manufact.

Code

VIL VIL VIH

VIH

VIL VID

Word-

wide

Device

Code

M28F410 VIL VIL VIH

M28F420 VIL VIL VIH

VIH

VIH VID

VIH

VIH VID

Don’t

Care

Don’t

Care

Don’t

Care

Manufact.

Code

VIL VIL VIH

VIL

VIL VID

Byte-

wide

Device

M28F410 VIL VIL VIH

VIL

VIH VID

Code

M28F420 VIL VIL VIH VIL VIH VID

Note: RP = VIH

Don’t

Care

Don’t

Care

Don’t

Care

DQ0 -

DQ7

20h

0F2h

0FAh

20h

0F2h

0FAh

DQ8 - DQ15

DQ14 A-1

00h

0

00h

0

00h

0

Hi-Z

Don’t

Care

Hi-Z

Don’t

Care

Hi-Z

Don’t

Care

DESCRIPTION

The M28F410 and M28F420 FLASH MEMORIES

are non-volatile memories that may be erased

electrically at the block level and programmed by

byte or word. The interface is directly compatible

with most microprocessors. SO44 and TSOP56

packages are used.

Organization

The organization, as 512K x 8 or 256K x 16, is

selectable by an external BYTE signal. When

BYTE is Low and the x8 organization is selected,

the Data Input/Outputsignal DQ15 acts as Address

line A-1 and selects the lower or upper byte of the

memory word for output on DQ0-DQ7, DQ8-DQ14

remain high impedance. When BYTE is High the

memory uses the Address inputs A0-A17 and the

Data Input/OutputsDQ0-DQ15. Memory control is

provided by Chip Enable, Output Enable and Write

Enable inputs. A Reset/Power Down/Boot block

unlock, tri-level input, places the memory in deep

power down, normal operation or enables pro-

gramming and erasure of the Boot block.

3/38

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