MT28S4M16B1LLFG-10 Ver la hoja de datos (PDF) - Micron Technology
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MT28S4M16B1LLFG-10 Datasheet PDF : 58 Pages
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When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1–A7 when the burst length is set to two, by
A2–A7 when the burst length is set to four, and by A3–
A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) are used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.
Figure 1
Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
111 10 9 8 7 6 5 4 3 2 1 0
Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Program M11,
M10 = “0, 0†to
ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0 Operating Mode
0
0
Defined Standard Operation
-
-
-
All other states reserved
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Table 1
Burst Definition
Burst
Length
2
4
8
Full
Page
256
StartingColumn Order of Accesses Within a Burst
Address
Type=Sequential Type=Interleaved
A0
0
0-1
0-1
1
1-0
1-0
A1 A0
00
0-1-2-3
0-1-2-3
01
10
1-2-3-0
2-3-0-1
1-0-3-2
2-3-0-1
11
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
010
011
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
101
110
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
n = A0–A7
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
Not supported
(location 0-255)
…Cn-1,
Cn...
NOTE:
1. For a burst length of two, A1–A7 select the block-
of-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A7 select the block-
of-four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A7 select the
block-of-eight burst; A0–A2 select the starting
column within the block.
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0–A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4,
or 8 words) is supported (not full page).
8. The contents of the mode register can be read
using the READ DEVICE CONFIGURATION command
(004h).
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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