AS8F512K32 Ver la hoja de datos (PDF) - Austin Semiconductor

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AS8F512K32

512K x 32 FLASH FLASH MEMORY ARRAY

Austin Semiconductor 

Austin Semiconductor, Inc.

FLASH

AS8F512K32

Operation Status Flags1 Table

Device Operations2

DQ7 DQ6 DQ5 DQ4

Byte-programming in progress

D\ T 0 X

Byte-programming exceed time limit D\ T 1 X

Byte-programming complete

DDDD

Sector/chip erase in progress

0T0X

Sector/chip erase exceed time limit

0T1X

Sector/chip erase complete

1111

DQ3

0

0

D

1

1

1

DQ2

X

X

D

X

X

1

DQ1

X

X

D

X

X

1

DQ0

X

X

D

X

X

1

NOTES:

1. T= toggle, D=data, X=data undefined

2. DQ4, DQ2, DQ1, DQ0 are reserved for future use.

OPERATION STATUS

Status Bit Definition

During operation of the automatic embedded program and

erase functions, the status of the device can be determined by

reading the data state of designated outputs. The data-polling

bit (DQ7) and toggle-bit (DQ6) require multiple successive reads

to observe a change in the state of the designated output.

Operation Status Flags Table defines the values of the Flag

status.

Data-Polling DQ7

The data-polling status outputs the complement of the data

latched into the DQ7 data register while the write-state machine

is engaged in a program or erase operation. Data bit DQ7 chang-

ing from complement to true indicates the end of an operation.

Data-polling is available only during the byte-programming,

chip-erase, sector-erase, and sector-erase timing delay. Data-

polling is valid after the rising edge of ?W/E in the last bus cycle

of the command sequence loaded into the command register.

During a byte-program operation, reading DQ7 outputs

the complement of the DQ7 data to be programmed at the se-

lected address location. Upon completion, reading DQ7 out-

puts the true DQ7 data loaded into the program data register.

During the erase operations, reading DQ7 outputs a 0. Upon

completion, reading DQ7 outputs a 1. Also, data polling must

be performed at a new sector address that is within a sector

being erased; otherwise the status is not valid. When using

data-polling, the address should remain stable throughout the

operation.

During a data-polling read, while ?W/E is low, data bit DQ7

can change asynchronously. Depending on the read timing,

the system can read valid data on DQ7, while other DQ pins are

still invalid. A subsequent read of the device is valid.

Data-Polling DQ6

The function of toggle-bit status, is to output data on

DQ6 that toggles between 1 and 0 while the write-state ma-

chine is engaged in a program or erase operation. When toggle-

bit DQ6 stops toggling after two consecutive reads to the same

address, the operation is complete. The toggle-bit is only

available during the byte-programming, chip-erase, and sector-

erase timing delay. Toggle-bit data is valid after the raising

edge of ?W/E in the last bus cycle of the command sequence

loaded into the command register. Depending on the read tim-

ing, DQ6 can stop toggling while other DQ pins are still invalid.

A subsequent read of the device is valid.

Exceed Time Limit DQ5

The program and erase operations use an internal pulse

counter to limit the number of pulses applied. If the pulse count

limit is exceeded, DQ5 is set to a 1 data state. This indicates that

the program or erase operation has failed. DQ7 will not change

from complemented data to true data and DQ6 will not stop

toggling when read. To continue operation, the device must be

reset.

This condition occurs when attempting to program a logic

1 state into a bit that has been programmed previously to a

logic 0. Only an erase operation can change bits from 0 to 1.

After reset, the device is functional and can be erased and

reprogrammed.

Sector-Load- Timer DQ3

DQ3 is the sector-load timer status bit it determines if the

time to load additional sector addresses has expired. DQ3 re-

mains a logic low for 80 µs after completion of a sector-erase

sequence. This indicates another sector-erase command se-

quence can be issued. If DQ3 is at logic high, it indicates that

the delay has expired and attempts to issue additional sector-

erase commands are ignored.

The data polling bit and toggle bit are valid during the 100

µs time delay and can be used to determine if a valid sector

erase command has been issued. To ensure additional sector

erase commands have been accepted, the status of DQ3 should

be read before and after each additional sector-erase command.

If DQ3 is at a logic low on both reads, then the additional sec-

tor-erase was accepted.

AS8F512K32

Rev. 5.2 09/07

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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