5962F-0323502QUA Ver la hoja de datos (PDF) - Aeroflex UTMC
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5962F-0323502QUA Datasheet PDF : 23 Pages
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A0
1
A1
2
A2
3
A3
4
A4
5
E1
6
DQ0
7
DQ1
8
VDD1
9
VSS
10
DQ2
11
DQ3
12
W
13
A5
14
A6
15
A7
16
A8
17
A9
18
36
E2
35
A18
34
A17
33
A16
32
A15
31
G
30
DQ7
29
DQ6
28
VSS
27
VDD1
26
DQ5
25
DQ4
24
A14
23
A13
22
A12
21
A11
20
A10
19
VDD2
Figure 2. 15ns SRAM Pinout (36)
PIN NAMES
A(18:0) Address
DQ(7:0) Data Input/Output
E1 Chip Enable 1
(active low)
E2 Chip Enable 2
(active high)
W WriteEnable
G Output Enable
VDD1 Power (1.8V)
VDD2 Power (3.3V)
VSS Ground
DEVICE OPERATION
The UT8R512K8 has four control inputs called Chip Enable 1
(E1), Chip Enable 2 (E2), Write Enable (W), and Output Enable
(G); 19 address inputs, A(18:0); and eight bidirectional data
lines, DQ(7:0). E1 and E2 device enables control device
selection, active, and standby modes. Asserting E1 and E2
enables the device, causes IDD to rise to its active value, and
decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
W E2 E1 I/O Mode Mode
X
X
X
1 3-state
Standby
X
X
0
X 3-state
Standby
X
0
1
0 Data in Write
1
1
1
0 3-state
Read2
0
1
1
0 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W and E2 greater than VIH (min) and E1 less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of chip enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as chip enable
and output enable are active, the address inputs may change at
a rate equal to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified tETQV is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is tGLQV unless tAVQV or tETQV have not been
satisfied.
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