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M27C512

512 Kbit (64K x8) UV EPROM and OTP EPROM

STMicroelectronics 

M27C512

DEVICE OPERATION

The modes of operations of the M27C512 are list-

ed in the Operating Modes table. A single power

supply is required in the read mode. All inputs are

TTL levels except for GVPP and 12V on A9 for

Electronic Signature.

Read Mode

The M27C512 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, indepen-

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

(tAVQV) is equal to the delay from E to output

(tELQV). Data is available at the output after a delay

of tGLQV from the falling edge of G, assuming that

E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27C512 has a standby mode which reduces

the active current from 30mA to 100µA The

M27C512 is placed in the standby mode by apply-

ing a CMOS high signal to the E input. When in the

standby mode, the outputs are in a high imped-

ance state, independent of the GVPP input.

Table 2. Operating Modes

Mode

Read

Output Disable

Program

Program Inhibit

Standby

Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

E

VIL

VIL

VIL Pulse

VIH

VIH

VIL

GVPP

VIL

VIH

VPP

VPP

X

VIL

A9

Q7-Q0

X

Data Out

X

Hi-Z

X

Data In

X

Hi-Z

X

Hi-Z

VID

Codes

Table 3. Electronic Signature

Identifier

A0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0 Hex Data

Manufacturer’s Code

VIL

0

0

1

0

0

0

0

0

20h

Device Code

VIH

0

0

1

1

1

1

0

1

3Dh

Two Line Output Control

Because EPROMs are usually used in larger

memory arrays, the product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power

dissipation,

b. complete assurance that output bus

contention will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

devices. The supply current, ICC, has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at

the output. The associated transient voltage peaks

can be suppressed by complying with the two line

output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceram-

ic capacitor be used on every device between VCC

and VSS. This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

6/22

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