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M24512-WMW

512 Kbit and 256 Kbit Serial I²C bus EEPROM with three Chip Enable lines

STMicroelectronics 

Summary description

M24512-W, M24512-R, M24256-BW, M24256-BR

1

Summary description

The M24512-W, M24512-R, M24256-BW and M24256-BR devices are I2C-compatible

electrically erasable programmable memories (EEPROM). They are organized as 64 Kb × 8

bits and 32 Kb × 8 bits, respectively.

I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.

The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the

I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a Device Select Code and Read/Write

bit (RW) (as described in Table 2), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages.

ECOPACK® packages are Lead-free and RoHS compliant.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 1. Logic diagram

VCC

3

E0-E2

SCL

WC

M24512-W

M24512-R

M24256-BW

M24256-BR

SDA

VSS

Table 1. Signal names

E0, E1, E2

SDA

SCL

WC

VCC

VSS

Chip Enable

Serial Data

Serial Clock

Write Control

Supply Voltage

Ground

AI02275c

6/31

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