M24256-BRBN6 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

M24256-BRBN6

512 Kbit and 256 Kbit serial I²C bus EEPROM with three Chip Enable lines

STMicroelectronics 

M24512-x, M24256-Bx

Signal description

2.5

VSS ground

VSS is the reference for the VCC supply voltage.

2.6

2.6.1

2.6.2

2.6.3

2.6.4

Supply voltage (VCC)

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and Table 9).

In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line

with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC, the VCC rise time must not

vary faster than 1 V/µs.

Device reset

In order to prevent inadvertent write operations during power-up, a power on reset (POR)

circuit is included. At power-up (continuous rise in VCC), the device does not respond to any

instruction until VCC reaches the power on reset threshold voltage (this threshold is lower

than the minimum VCC operating voltage defined in Table 8 and Table 9). When VCC passes

over the POR threshold, the device is reset and enters the Standby Power mode. However,

the device must not be accessed until VCC reaches a valid and stable VCC voltage within the

specified [VCC(min), VCC(max)] range.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops

below the power on reset threshold voltage, the device stops responding to any instruction

sent to it.

Power-down conditions

During power-down (where VCC decreases continuously), the device must be in the Standby

Power mode (mode reached after decoding a Stop condition, assuming that there is no

internal Write cycle in progress).

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