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LXT9785

Advanced 8-Port 10/100 Mbps PHY Transceivers

Intel 

Contents

Revision Number: 007

Revision Date: August 28, 2003

Page Description

120 Modified/added text under Section 4.3.2, “Internal Loopback”.

121 Modified text under Section 4.3.6, “MII Isolate”.

Section 4.3.7, “MDIO Management Interface”:

121 Added note under second paragraph.

Added last paragraph.

123 Added note under Section 4.3.8, “MII Sectionalization”.

124 Added new Section 4.3.11, “FIFO Initial Fill Values”

125 Modified paragraph three under Section 4.4.1, “Power Requirements”.

127 Added notes under second and last paragraphs under Section 4.5.3, “Power-Down Mode”.

128 Modified last bullet under Section 4.5.3.1, “Global (Hardware) Power Down”.

128 Added last paragraph to Section 4.5.4, “Reset”.

129 Modified Table 42 “Intel® LXT9785/9785E Global Hardware Configuration Settings”.

130 Change heading and modified last line under Section 4.6.1.2, “Manual Next Page Exchange”.

Section 4.6.1.4, “Link Criteria”:

130

Changed scrambler to descrambler in first line.

Modified second paragraph.

Added two new paragraphs.

131 Added second paragraph under Section 4.6.1.5, “Parallel Detection”.

131

Modified paragraphs under Section 4.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is

Enabled in Forced Speed Mode”.

136 Changed “1110” to “0101” under Section 4.7.4.3, “Receive Error”.

141 Added note under first paragraph of Section 4.8, “RMII Operation”

148

Changed “asynchronously” to “synchronously” in second paragraph under Section 4.9.3.3, “Carrier

Sense/Data Valid (RMII)”.

148 Modified last sentence in first paragraph under Section 4.9.3.4, “Carrier Sense (SMII)”.

149 Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.

149 Added note under Section 4.9.3.7, “Fiber PMD Sublayer”.

149 Added second paragraph under Section 4.9.3.7.1, “Far End Fault Indications”.

150 Modified/added text under Section 4.10.1, “Preamble Handling”.

151 Modified text under Section 4.10.4, “Jabber”.

152 Modified first paragraph under Section 4.11, “DTE Discovery Process”.

153 Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.

154 Modified second paragraph under Section 4.11.4, “DTE Discovery Process Flow”.

155 Added Section 4.11.5, “DTE Discovery Behavior”

157

Added BGA15 information into first paragraph under Section 4.12.2, “Per-Port LED Driver

Functions”.

158

Added last sentence to first paragraph and note under first paragraph under Section 4.12.3, “Out-of-

Band Signaling”.

160 Added Section 4.13, “Cable Diagnostics Overview”.

161 Modified/added text under Section 4.13.3, “Implementation Considerations”.

Datasheet

11

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

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