LX1688 Ver la hoja de datos (PDF) - Microsemi Corporation
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LX1688 Datasheet PDF : 16 Pages
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RangeMAX™
LX1688
TM
®
Multiple Lamp CCFL Controller
PRODUCTION DATA SHEET
DETAILED DESCRIPTION
and may or may not be externally synchronized to the LCD
video frame rate. It will directly gate the signal BRT.
CPWM should not be used in this case.
FAULT PIN
The fault pin is a digital output that indicates that the
maximum numbers of strike attempts has occurred without
lamp ignition. In this condition the FAULT pin will go
active high with typically 20mA drive capability. Holding
the OLSNS pin low (<200mV) will also force timeout and
activate the FAULT pin. When used as a master, fault
condition true does not inhibit master clock outputs
PHA_SYNC and RMP_RST.
I_R PIN
The run mode frequency of the output is one half the
internal ramp frequency, which is proportional to a bias
current set by resistor RI of 80.6K. The output frequency
can thus be adjusted by varying the value of RI-R, the
typical range from about 50K to 100K. Since there is some
variation in the frequency due to change in the input supply
(VDD) it is recommended that the value of RI-R be selected
at the nominal input voltage.
SLEEP MODE (ENABLE SIGNAL) AND SWITCHED VDD
(VDDSW)
Since the LX1688 can be used in portable battery
operated systems, a very low power sleep mode is included.
The IC will consume less than 10µA quiescent current from
both the VDD and VDD_P pins combined, when the
ENABLE pin is deactivated. The polarity of the ENABLE
pin is programmable by the BEPOL input (see table 1). In
addition the controller provides a switched supply pin
VDDSW this output supplies at least 10mA at VDD ─ .2V
for external circuitry. This output can be used to power
additional circuitry that can be enabled with the controller.
RMP_RST AND PHA_SYNC PIN TIMING REQUIREMENT
WITH SLAVE MODE OPERATION
When the LX1688 is configured for slave mode
operation, and RMP_RST and PHA_SYNC is supplied
from an external source, the signal timing should be met as
outlined below.
RMP_RST should be 2 times frequency of lamp
frequency and duty should be 10 to 13%, and PHA_SYNC
should be generated by divide by 2 of RMP_RST signal.
Phase of these signals should be met the as shown, note the
delay between the RMP_RST and PHA_SYNC signals:
Min Typ Max
T1
150 250
T2
10
13
T3
49
50
51
Tr, Tf
100
T3 duty is 50% of operating frequency.
Unit
nsec
%
%
nsec
T2
T3
T1
BIAS & TIMING EQUATIONS
Formula 1:
Formula 2:
Triangular Wave Generator Frequency, FTRI
FTRI =
1
[Hz]
(25× RI × CTRI )
Lamp Frequency (AOUT’s switching frequency), FLAMP
FLAMP =
1
[Hz]
200e-12× RI
Formula 3:
Formula 4:
Minimum Current Error Amp Bandwidth, BWIEA_MIN
BWIEA_MIN = 0.000048 [Hz]
CICOMP
Minimum Voltage Error Amp Bandwidth, BWVEA_MIN
BWVEA_MIN = 0.000048 [Hz]
CVCOMP
Formula 5:
Softstart time, TSS
TSS = 4,500,000 × CVCOMP [sec]
Formula 6:
Minimum Power-on Reset Pulse Width, TMIN_POR
TMIN_POR = 2.3e6 × CPOR [sec]
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
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