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LX1684 Datasheet PDF : 12 Pages
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LX1684
TM
®
Voltage-Mode PWM Controller
PRODUCTION DATA SHEET
APPLICATION INFORMATION
SOFT-START CAPACITOR (continued)
The capacitor current to follow the SS-pin voltage is:
ICOUT = COUT dV = COUT × e−(t / RSSCSS )
dt CSS
where COUT is the output capacitance. The typical value of CSS
should be in the range of 0.1 to 0.2µF.
During the soft-start interval the load current from a
microprocessor is negligible; therefore, the capacitor current is
approximately the required inductor current.
OVER-CURRENT PROTECTION
Current limiting occurs at current level ICL , when the voltage
detected by the current sense comparator is greater than the current
sense comparator threshold, VTRIP (400mV).
ICL × RDS (ON ) + ISET × RSET = VTRIP
So,
RSET = VTRIP − ICL × RDS (ON )
ISET
RSET = 400mV − ICL × RDS (ON )
45µA
Example:
For 10A current limit, using SUB45N05-20L MOSFET (20mΩ
RDS(ON) ):
RSET
=
0.4 − 10 × 0.020
45 ×10−6
=
4.42kΩ
Current Sensing Using Sense Resistor
The method of current sensing using the RDS(ON) of the upper
MOSFET is economical, but can have a large tolerance, since the
RDS(ON) can vary with temperature, etc. A more accurate alternative
is to use an external sense resistor (RSENSE ). The sense resistor
could be a PCB trace (for construction details, see Application
Note AN-10 or LX1668 data sheet). The over-current trip point is
calculated as in the equations above, replacing RDS(ON) with RSENSE .
Example:
For 10A current limit, using a 5mΩ sense resistor:
RSET = VTRIP − (ICL × RSENSE)
ISET
RSET
=
0.4 −10× 0.005
45 ×10−6
=
7.8kΩ
OUTPUT ENABLE
The LX1684 FET driver outputs are driven to ground by pulling
the soft-start pin below 0.3V.
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage is sensed by the feedback pin (V FB ) which
has a 1.25V reference. The output voltage can be set to any voltage
above 1.25V (and lower than the input voltage) by means of a
resistor divider (see Product Highlight).
VOUT = VREF (1+ R1 )
R2
Note: Keep R 1 and R 2 close to 100Ω (order of magnitude).
FET SELECTION
To insure reliable operation, the operating junction temperature
of the FET switches must be kept below certain limits. The Intel
specification states that 115°C maximum junction temperature
should be maintained with an ambient of 50°C. This is achieved by
properly derating the part, and by adequate heat sinking. One of the
most critical parameters for FET selection is the RDS(ON) resistance.
This parameter directly contributes to the power dissipation of the
FET devices, and thus impacts heat sink design, mechanical layout,
and reliability. In general, the larger the current handling capability
of the FET, the lower the R DS(ON) will be, since more die area is
available.
TABLE 1 - FET Selection Guide
This table gives selection of suitable FETs from VISHAY
Device
VDS
(V)
RDS(ON)
@4.5V
(mΩ)
RDS(ON)
@10V
(mΩ)
D2PAK and TO-220
SUB70N03-09BP 30
13
9
SUB45N03-13L
30
20
13
SUB45N05-20L
40
20
18
SUB70N04-10
40
14
10
SO-8
Si4810DY
30
20
13.5
Si4812DY
30
28
18
Gate
Charge
typ(nC)
15.5
45
43
50
20
16
Heat Dissipated In Upper MOSFET
The heat dissipated in the top MOSFET will be:
PD = (I 2 × RDS (ON ) × Duty Cycle) + (0.5 × I ×VIN × tSW × fS)
Where tSW is switching transition line for body diode (~100ns) and
fS is the switching frequency.
For the SUB70N03-09BP (13mΩ RDS(ON) ), converting 12V to
3.3V at 15A will result in typical heat dissipation of 2.6W.
Copyright © 2000
Rev. 1.0c, 2005-03-08
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
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